What we do at the Computer Systems Research Laboratory

The Computer Systems Research Laboratory is a research group made up of faculty members and students in the Department of Computer Science and Engineering at the University of North Texas. While we are interested in many topics within computer science, our current research focuses mainly on multithreaded architectures and compiler optimization.

UNT Research Park

Hardware/Software Co-Design

Using hardware/software co-design to create automated tools converting procedural programming languages into hybrid architectures

When customized, hybrid processors have higher performance and power than generic processor, while remaining flexible. The problem hybrid processors currently face is that the available customizing tools require substantial knowledge of the hardware. Our solution is to create automated customizing tools.

Using the concept of hardware/software co-design, we are developing a compiler that converts C code into general-purpose CPU and FPGA code based upon hardware specifications and performance requirements. While the goal of current hardware/software co-design is to create hybrid hardware specifically optimized for a single application, our goal is to map applications written in a procedural programming language to a hybrid architecture that has already been specified.

Scheduled Dataflow (SDF) architecture

Through optimizations such as compile time and predicted instructions, we are enhancing our Scheduled dataflow architecture.

We have developed a new dataflow, Scheduled Dataflow (SDF), which uses a simpler, yet more powerful, execution paradigm than what the recent trend in processor architecture can offer.

SDF architecture has a decoupled memory/execution multithreaded architecture in which it is easier to coordinate memory access and execution of a thread than in regular control-flow architectures. The functional nature of SDF's instructions eliminates the need for dynamic scheduling of instructions within a thread; it executes instructions synchronously with no Write-After-Write or Write-After-Read dependencies.

We are now working on developing SDF enhancements, including predicted instructions, compile-time optimization, operand memory reuse, and speculative pre-loading of thread contexts.

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