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Publications on FPGA Physical Design and Synthesis

Below you can find a list of publications related to our research in FPGA physical design and synthesis.

• 1. Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, and Xianlong Hong, ''New Timing and Routability Driven Placement Algorithms for FPGA Synthesis," to appear in GLSVLSI 2007. PDF
• 2. Yue Zhuo and Hao Li, ''A Novel Timing and Congestion Driven Algorithm for FPGA Placement,'' to appear in Proceedings International Symposium on Field-Programmable Gate Arrays 2007.
• 3. Yue Zhuo, Hao Li, and Saraju Mohanty, ''A Congestion Driven Placement Algorithm for FPGA Synthesis,'' in Proceedings of International Conference on Field Programmable Logic and Applications, pp. 683-686, August 2006. PDF
• 4. Hao Li, Srinivas Katkoori, and Zhipeng Liu, ''Feedback Driven High Level Synthesis for Performance Optimization,'' in Proceedings of 6th International Conference on ASIC, pp. 882-885, October 2005. PDF
• 5. Wai-Kei Mak, and Hao Li, ''Modern FPGA Placement,'' in Proceedings of Emerging Information Technology Conference, August 2005, Taiwan. PDF
• 6. S. Mohanty, R. Velagapudi, V. Mukherjee, and Hao Li, ''Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits,'' in Proceedings of ISVLSI 2005, pp.248-249, May 2005. PDF
• 7. Hao Li, Wai-Kei Mak, and Srinivas Katkoori, ''Power Minimization Algorithms for LUT Based FPGA Technology Mapping,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.9, No.1, pp. 33-51, January 2004.
• 8. Hao Li, Srinivas Katkoori, and Wai-Kei Mak, ''Force-directed Performance Driven Placement Algorithm for FPGAs,'' in Proceedings of ISVLSI 2004, pp.193-198, Feburary 2004.
• 9. Hao Li, Wai-Kei Mak, and Srinivas Katkoori, ''An Efficient LUT-Based FPGA Technology Mapping Algorithm for Power Minimization,'' in Proceedings of ASP-DAC, pp.353-358, January 2003. (Nominated for Best Paper Award) PDF
• 10. Hao Li, Wai-Kei Mak, and Srinivas Katkoori, ''LUT-based FPGA Technology Mapping for Power Minimization with Optimal Depth,'' in Proceedings IEEE WVLSI 2001 , pp.123-128, April 2001. PDF