Intelligent Memories and Memory Management

In this research we are investigating the use of separate hardware devices for the purpose of off-loading some functions from CPU.

We are also looking at optimizing cache memories for embedded systems. One idea we have been exploring is the use of separate data caches at Level 1, so that different types of data can be cached in different regions. It is then possible to explore reconfigurable designs whereby cache can be configured to specific applications to improve performance and reduce energy consumed while executing the applications.

More specifically we are looking to off-load memory management functions including memory allocation/deallocation, garbage collection, jump pointers and address forwarding functions to the logic on memory chips available with IRAM and PIM devices.

Our initial studies have concerntrated on the impact of off-loading memory allocation functions on the CPU cache performance, since the allocation functions will no longer pollute the CPU cache.

In this research we are also studying various allocator and garbage collection techniques that are suitable for execution by a dedicated hardware unit.

Related Papers

A. Naz, K. Kavi, W. Li and Philip Sweany. "Tiny split data caches make big performance impact for embedded applicationsā", Journal of Embedded Computing (IOS Press), Vol. 2, No. 2 (May 2006). in pdf

M.Rezaei and K.M. Kavi. "Elimination of Cache Pollution Due to Memory Management using an Intelligent Memory Managerā", Journal of Systems Architecture (published by Elsevier), January 2006, Volume 52, No.1, pp 41-55. in pdf

A. Naz, M. Rezaei, K.Kavi and P. Sweany. "Improving Data Cache Performance With Integrated Use Of Split Caches, Victim Cache And Stream Buffers", Proceedings of the Workshop on Memory performance dealing with applications, systems and architecture (MEDEA-2004), held in conjunction with Parallel Architectures and Compiler Technology (PACT-2004) Conference, Sept. 29-Oct. 3, 2004, Antibes Juan-Les-Pins, France. in pdf

A. Naz, K.M. Kavi, P.H. Sweany and M. Rezaei. "A study of separate array and scalar caches" Proceedings of the 18th International Symposium on High Performance Computing Systems and Applications (HPCS 2004), Winnipeg, Manitoba, Canada, May 16-19, 2004, pp 157-164. in pdf

M. Reezaei and K.M. Kavi. "Utilization of Separate Caches to Eliminate Cache Pollution Caused By Memory Management Functions", Proceedings of the 16th International Conference on Parallel and Distributed Computing Systems (PDCS-2003, sponsored by the International Society for Computers and their Applications, ISCA), Aug. 3-15, Reno, Nevada, USA. in pdf

S. Donahue, M.P. Hampton, R. Cytron, M. Franklin and K.M. Kavi. "Hardware support for fast and bounded time storage allocation", Proceedings of the Workshop on Memory Processor Interfaces (WMPI), in conjunction with the International Symposium on Computer Architecture, May 2002, Anchorage, Alaska, pp . in pdf

S.M. Donahue, M.P. Hampton, M. Deters, J.M. Nye, R.K. Cytron and K.M. Kavi. "Storage Allocation for real-time, embedded systems", Proceedings of the First International Workshop on Embedded Software (Washington, DC, May 2001), Springer Verlag, pp 131-147 in pdf

K.M. Kavi, M. Rezaei and R. Cytron. "An efficient memory management technique that improves localities", Proc. International Conference on Advanced Computing and Communications (ADCOM 2000), Cochin, India, Dec. 15-17, 2000. in pdf

M. Rezaei and K.M. Kavi. "A new implementation for memory management", Proceedings of the IEEE Southeastcon 2000 Conference, April 7-9, 2000, Nashville, TN. In PDF